III-V/InP bonding on Silicon | SCINTIL Photonics

TECHNOLOGY: III-V/InP bonding on Silicon

Our unique approach, called BackSide-on-BOX, enables seamless integration of lasers and optical amplifiers by combining Si and InP/III-V materials. Our technology solve the pain of standard silicon photonics lacking lasers.

Unprocessed InP/III-V dies are bonded on the backside of processed wafers, only where it is needed. Our fabrication process is CMOS-compatible and relies on the standard silicon-photonics process.

This technology enables to produce and monolithically integrate DFB lasers and SOAs, Si modulators, Ge-waveguide photodetectors, SiN and Si devices.

FABRICATION STEPS: III-V/InP Integration steps with Silicon Photonics

Step 1: Silicon Photonics Processing

Step 2: Dies-to-Wafer Bonding

Step 3: III-V material patterning

Step 4: Electrical Contacts

The silicon wafer is fabricated according to standard SiPho processes available in commercial foundries for SOI wafer comprising a Buried OXide (BOX) layer and a top Si layer.

The top Si layer is etched for defining the Si waveguides and other optical elements such as modulators, multiplexers, and demultiplexers.

Photo Diodes can be formed by using epitaxial deposited of Germanium (Ge), and Silicon Nitride (SiNx) can be added to form low-loss, high-performance passive devices.

The SiPho-processed wafer is then flip-bonded onto a new Si handle. The original Si substrate is removed, leaving the BOX layer on top.

Unprocessed InP dies with gain epitaxial layers are bonded onto the exposed BOX layer wherever a laser source, amplifier or modulator is required.

The dies bonding step does not require a precise alignment as the epitaxial layers are not patterned yet.

InP substrate of the dices is the removed to leave only the gain epi-layers bonded on the BOX.

Finally, the gain layers are etched at the wafer level to define the lasers’ waveguides.

Electrical contacts are then added following CMOS-compatible process.

At the end of the manufacturing flow, there is chemical-mechanical planarization for allowing flip-chip or wire-bond of high-speed electronic integrated circuits..