Technology

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Our unique approach, called BackSide-on-BOX, enables seamless and extensive integration of active and passive optical components by combining Si and InP/III-V materials.

Unprocessed InP/III-V dies are bonded on the backside of processed Silicon-On-Insulators (SOI) wafers, only where it is needed. Our fabrication process is CMOS-compatible and relies on the standard silicon-photonics process. Our optical component library includes lasers (WDM laser arrays & tunable lasers), modulators, SOA, waveguides, wavelength filters, surface fiber couplers, and photodetectors.

FABRICATION STEPS

BENEFITS

PERFORMANCE
AND
RELIABILITY

High-coupling efficiency of lasers in the waveguide
No alignment of lasers needed
Optical amplification on-chip
High-speed modulator with low insertion loss
Intrinsic hermetic design

FEATURE-RICH

IN A COMPACT FORM FACTOR

All-optical components in one-chip, including lasers
Germanium (Ge) for efficient photodetector
Silicon Nitride (SiNx) for improved passive devices

COST OPTIMISED

FOR VOLUME

Production in commercial foundry
Wafer-level lasers integration & test
Flip-chip assembly for Electronic IC
No hermetic package needed

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1- SiPho
Processing

The SiP wafer is fabricated according to standard SiP processes available in commercial foundries on an SOI wafer comprising the original Si substrate, the Buried OXide (BOX) layer, and the top Si layer.

The top Si layer is etched for defining the Si waveguides and other optical elements such as modulators, multiplexers, and demultiplexers.

Ge PDs can be formed by using epitaxial deposited Ge, and SiNx can be added to form low-loss, high-performance passive devices.

2 - Molecular
Bonding

The SiP-processed wafer is then flip-bonded onto a new Si handle.

The original Si substrate is removed, leaving the BOX layer on top.

Unprocessed InP dies with gain epitaxial layers are bonded onto the exposed BOX layer wherever a laser source, amplifier or modulator is required.

The bonding step does not require any precise alignment as the epitaxial layers are not processed yet.

3 - III-V material patterning

InP or GaAs die substrates are removed to leave only the gain epi-layers on the BOX.

Finally, the gain layers are etched at the wafer level to define the lasers’ waveguides.

4 - Electrical Contacts

Electrical contacts are then made using materials and processes of CMOS-compatible foundries.

At the end of the manufacturing flow, there is a chemical mechanical planarization to enable the integration with electronic ICs .

The latter can be flip chip assembled on the PIC surface according to standard packaging technology.

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CONTACT US

SCINTIL Photonics

BHT – Bât. 52

7, parvis Louis Néel – CS 20050

38040 Grenoble cedex 09

France

TECHNOLOGY